Semiconductor device including stacked chips having metal patterned on circuit surface and on edge side of chip
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United States of America Patent
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Apr 6, 1999
Grant Date -
N/A
app pub date -
Aug 18, 1997
filing date -
Aug 18, 1997
priority date (Note) -
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Abstract
A three-dimensional semiconductor circuit assembly wherein each of several circuit chips is provided with patterned metal layers that extend from the circuit surface onto an edge side of the chip, then the chips are adhesively bonded to opposite surfaces of one or more dielectric spacers, respectively, whereby the edge sides of the resulting multiple-chip stack are readily connected to metal patterns on a substrate.
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