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Abstract

A VLAN memory access system to provide VLAN address table look-ups with the ability to simultaneously do processor read cycles or processor write cycles to the same memory structure with anatomical accesses. The system encompasses the interaction between a memory look-up table that stores the slot allowed transition bit mask for a multi-slot hub based VLAN switch, a switch processor interface that is used to upgrade the memory access table by writing entries into the table or reading the table to verify its contents, and a look-up processor that uses the VLAN table to make forwarding decisions on the destination of a packet based on the value read from the VLAN memory look-up table. The VLAN table accesses must be arbitrated between the look-up processor, which has the highest priority, and read or write accesses from the switch processor. The look-up processor takes the VLAN ID field of a packet and uses this as the address of the slot allowed transmit bit mask to be applied to the destination slot bit mask. This logical AND function is used to determine the final bit mask of slots that will receive this packet.

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First Claim