Field programmable gate array having programming instructions in the configuration bitstream
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United States of America Patent
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Apr 6, 1999
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N/A
app pub date -
Aug 29, 1997
filing date -
Feb 17, 1995
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Abstract
A programmable gate array (FPGA) comprises a CPU coupled to a configuration memory array. Bitstream data used for configuring the configuration memory array is encoded to combine programming instructions and configuration data. The CPU receives and decodes the encoded bitstream data, and executes the programming instructions to efficiently load configuration data into the configuration memory array. For instance, configuration data can be temporarily stored in the CPU and reused where data patterns in the configuration memory array repeat. Use of the programmable CPU for loading the configuration memory array reduces the amount of data transmitted to the FPGA during array configuration.
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