System for parallel port with direct memory access controller for developing signal to indicate packet available and receiving signal that packet has been accepted
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United States of America Patent
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-
Apr 6, 1999
Issued Date -
N/A
app pub date -
Apr 30, 1996
filing date -
Nov 3, 1989
priority date (Note) -
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status (Latency Note)
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Abstract
The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.
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