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Abstract

This disclosure provides a memory system and device for synchronizing response across multiple memory devices, whether arranged serially upon a single data bus, in parallel across multiple data busses, or both. A memory controller periodically configures the system by separately placing each memory chip into a configuration mode. While in this mode, the chip is polled by the controller along the corresponding data bus, and the chip responds with a reply. The controller uses this reply to compute elapsed time between polling and the reply. Using all of the chips, the controller determines the maximum response time, in terms of elapsed clock cycles. Based on this maximum time, and the individual response times for each chip, the controller then programs each chip with a number which defines chip-based delay for responses to data read operations. In this manner, successive data reads can be performed on successive clock cycles without awaiting prior completion of earlier data reads. In addition, in a multiple data bus system, the controller is not delayed by having to wait for all simultaneous data reads across a wide bus. The disclosure provides a memory system for dealing with response skew over integer clock cycles and can be used with other systems for synchronizing clock cycle phase across multiple memory devices, for example, as set forth by U.S. Pat. No. 4,998,262.

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First Claim