Parallel processing unit with cache memories storing NO-OP mask bits for instructions
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United States of America Patent
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Apr 6, 1999
Grant Date -
N/A
app pub date -
Jun 21, 1996
filing date -
Jun 28, 1995
priority date (Note) -
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Abstract
Each processing unit 110a to 110d has an individual cache memory 100a to 100d. When the cache memories read an instruction from a main storage 5, an instruction field is distributed to the cache memories. Each cache memory is controlled by a common control circuit 20. A compiler operates to schedule the processes so as to focus the processes to be executed on a specific processing unit. According to the scheduled processes, the volumes of the cache memories 100a to 100d are specified according to each execution ratio of the corresponding processing units to the cache memories. In the foregoing arrangement, a processor provides the processing units controlled by a sole program counter and improves processing by improving the efficiency of the cache memory. Further, the processor improves the efficiency of the cache memory by deleting unnecessary codes.
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