Method and apparatus for preventing a race condition and maintaining cache coherency in a processor with integrated cache memory and input/output control
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United States of America Patent
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Apr 6, 1999
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N/A
app pub date -
Aug 2, 1996
filing date -
Aug 2, 1996
priority date (Note) -
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Abstract
An integrated processor includes an on-chip integrated input/output (IO) system (which does not have a on-chip bus) to handle direct memory access (DMA) operations from external IO units and interface with external cache and main memories. The integrated IO system includes an external cache controller that controls access to both the cache and main memory so as to maintain coherency between the cache and main memory. As part of maintaining data coherency, the cache controller prevents race conditions between instructions generated from a core logic unit within the microprocessor and DMA instructions generated from an external IO unit by giving the DMA request priority over the CPU instructions.
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