Method for spawning two independent states in a state flow diagram
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United States of America Patent
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Apr 13, 1999
Issued Date -
N/A
app pub date -
Nov 14, 1997
filing date -
Jul 30, 1993
priority date (Note) -
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status (Latency Note)
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Abstract
A system and method for entering a circuit design into a computer using a schematic capture package. The schematic capture package is modified to include a library of state flow components represented by symbols which can be connected to produce a desired representation of the circuit design. The system allows a circuit design to be displayed on a video terminal using both state flow diagram and the schematic diagram symbols, with terminals of the state flow symbols connecting to terminals of the schematic symbols. The state flow diagram using state flow symbols is combined with a schematic diagram including schematic symbols to generate a netlist representing the combined circuit.
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