Nonvolatile semiconductor memory device and method of reducing read disturbance
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United States of America Patent
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Apr 13, 1999
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N/A
app pub date -
Jun 17, 1997
filing date -
Jun 19, 1996
priority date (Note) -
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Abstract
In a nonvolatile semiconductor memory device having a memory array of a NAND structure, threshold voltages of the word line voltage set at the time of reading are set to V.sub.WL00, V.sub.WL01, and V.sub.WL10, and one V.sub.WL10 among the threshold voltages is set to the negative voltage. By this, it becomes possible to set the threshold voltage distribution width of the memory transistor and the interval between one data and the next wider. As a result, writing control becomes easier and the disturbance/retention characteristics can be enhanced.
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