Semiconductor memory device equipped with an equalizing control circuit having a function of latching an equalizing signal
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United States of America Patent
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Apr 13, 1999
Grant Date -
N/A
app pub date -
Feb 26, 1997
filing date -
Feb 27, 1996
priority date (Note) -
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Abstract
The present invention relates to a semiconductor memory device which, while preventing an operation error, achieves the shortening of a precharging time and, hence, further shortening of a cycle time of a memory operation. The equalizing control circuit includes a latch circuit. An equalizing control circuit receives a signal WLact and a signal X-ADR from a predecoder and outputs an equalizing signal EQS from these two signals. A latch circuit in the equalizing control circuit is set (the inactivation of an equalizing signal) by a signal X-ADR which is activated with an internal RAS signal and holds its state. The latch circuit is reset (the activation of the equalizing signal) by a signal corresponding to a word line active signal WLact with a word line inactivated. By doing so, it is possible to provide the equalizing control circuit not directly depending upon the internal RAS signal.
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