Method and apparatus for controlling I/O channels responsive to an availability of a plurality of I/O devices to transfer data
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United States of America Patent
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Apr 13, 1999
Issued Date -
N/A
app pub date -
Aug 26, 1996
filing date -
Mar 17, 1995
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Abstract
An apparatus and method for improving the input/output performance of a computer system under the control of a multi-tasking, multi-threaded operating system. In particular, the invention provides an apparatus and method to chain contiguous DMA scatter gather sub blocks of a PRD table for channel 0 with contiguous DMA scatter gather sub blocks of a PRD table for channel 1, using a single data manager, while maintaining maximum media bandwidth. DMA block transfers are scheduled based on the availability of data from the I/O device's buffer memory, thus minimizing both media or network idle time as well as minimizing I/O bus idle time. Near maximum aggregate bandwidth of multiple I/O buses and their associated devices is obtained. The apparatus and method thus provides significant performance advantages over prior techniques having two I/O channel systems implemented with a single data manager.
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