Mechanism for enabling multi-bit counter values to reliably cross between clocking domains
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United States of America Patent
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Apr 13, 1999
Grant Date -
N/A
app pub date -
Sep 29, 1995
filing date -
Sep 29, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A queue structure for transmitting a multiple-bit signal from a first sub-system operating in a first clocking domain in a computer system to a second sub-system operating in a second clocking domain in the computer system is disclosed. The queue structure comprises a queue data latch having a plurality of storage elements, wherein each of the plurality of storage elements can store the multiple-bit signal from the first sub-system. A load pointer is used for generating a first multiple-bit count indicating one of the plurality of storage element for storing the multiple-bit signal. A synchronization unit is coupled to the load pointer for receiving the first multiple-bit count. The synchronization unit outputs the multiple-bit count at the second sub-system when the multiple-bit signal is ready to be sampled in the second clocking domain.
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