Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5895261
SERIAL NO

08873809

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A local area interconnect structure comprising one or more electrically conductive interconnects formed from electrically conductive metal compounds is described and a process for forming same. Electrically conductive metal compounds are selectively deposited in one or more trenches which were previously formed in an insulation layer in a configuration conforming to the desired pattern of the electrically conductive interconnects. A seed layer is first selectively formed on surfaces of the trenches and the electrically conductive metal compound is then selectively deposited over the seed layer in the trench, but not on the exposed surfaces of the insulation layer.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
BELL SEMICONDUCTOR LLC401 N MICHIGAN AVE SUITE 1600 CHICAGO IL 60611

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Sanganeria, Mahesh K Sunnyvale, CA 12 447
Schinella, Richard Saratoga, CA 17 365

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation