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Abstract

The invention relates to a computer implemented process for fixing hold time violations in hierarchical designs of electronic circuits. The process comprises the steps of: 1) synthesizing a RTL-HDL type description of the circuit to form a synthesized design, 2) synthesizing a clock tree and adding it to the synthesized design produced in step 1, 3) optimizing the synthesized design resulting from step 2, and fixing upper-bounded timing constraints by using a real clock timing (latency and skew) and worst case conditions, 4) fixing lower-bounded timing violations in the optimized synthesized design resulting from step 3, using a real clock timing, using best case conditions, 5) re-fixing possible upper-bounded timing constraints newly created and possible upper-bounded timing constraints increased in step 4, 6) fixing post-layout upper-bounded timing violations.

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First Claim