Multi-port random access memory with shadow write test mode
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United States of America Patent
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Apr 20, 1999
Issued Date -
N/A
app pub date -
Jul 24, 1997
filing date -
Jun 20, 1996
priority date (Note) -
Expired
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Abstract
Disclosed is an architecture of a RAM (random access memory) with BIST (built-in self test) or functional test function. The RAM has a memory cell for storing differential or single-ended binary data and bit line signals are fully differential or single-ended. Shadow write is applied to read only and read-write bit lines. With the test function, port-to-port bit line shorts and port-to-port word line shorts are sensitized.
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