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Abstract

A memory device. The memory device includes an array of word lines and complementary bit line pairs. A number of memory cells are each addressably coupled to intersections of the word line with a bit line of a complementary bit line pair. The memory device also includes addressing circuitry that is coupled to the array so as to select a memory cell. Further, a number of sense amplifiers are provided. Each sense amplifier is coupled to a complementary pair of bit lines. Each complementary pair of bit lines is also coupled to an equilibration circuit. A transistor controllably couples the reference voltage source to the equilibration circuit. The transistor is disabled when one of the bit lines of the complementary pair is defective so as to isolate the reference voltage source and prevent leakage current.

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First Claim