Method for encapsulating an integrated semi-conductor circuit
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United States of America Patent
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Apr 27, 1999
Grant Date -
N/A
app pub date -
Jun 10, 1997
filing date -
Jun 11, 1996
priority date (Note) -
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Abstract
Method for encapsulating an integrated semi-conductor circuit (die) comprising the following steps: a) mounting the semi-conductor circuit onto the surface of a so-called lead frame, b) attaching connecting wires between the contact surfaces of the semi-conductor circuit and selected parts of the lead frame (bonding operation), c) by means of a mould producing a plastic housing which at least encapsulates the semi-conductor circuit, the supporting surface, the bonding wires and part of the lead frame, d) the mould comprises an inwards extending section of which the end surface in the closed situation of the mould extends parallel to the free upper side of the integrated semi-conductor circuit at short distance thereof, and e) before closing the mould a layer of heat resistant deformable material in the form of a ring or a continuous layer is brought in between the upper side of the integrated semi-conductor circuit and said end surface of the inwards extending part, which layer not or hardly adheres to the plastic housing.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| SENCIO B V | 6534 AT NIJMEGEN |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Kaldenberg, Peter Jacobus | Nijmegen, NL | 2 | 155 |
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| Fee | Large entity fee | small entity fee | micro entity fee |
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| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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