Host I.sup.2 C controller for selectively executing current address reads to I.sup.2 C EEPROMs
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United States of America Patent
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Apr 27, 1999
Grant Date -
N/A
app pub date -
Dec 24, 1996
filing date -
Dec 24, 1996
priority date (Note) -
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status (Latency Note)
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Abstract
A computer system having a bridge and I.sup.2 C EEPROMs is provided with a host I.sup.2 C controller implemented in the bridge for accelerating the reading of the I.sup.2 C EEPROMs. The host I.sup.2 C controller accelerates the reading of I.sup.2 C EEPROMs by executing current address reads of the I.sup.2 C EEPROM when a requested slave address matches a current slave address stored in a current slave address register, and the requested EEPROM address matches a current EEPROM address stored in a current EEPROM address counter. The host I.sup.2 C controller thus eliminates the use of software to track the read accesses of a plurality of masters to an I.sup.2 C EEPROM and also eliminates the use of bus command protocols to support both random reads and current address reads to an I.sup.2 C EEPROM.
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