Importance

Loading Importance Indicators...

Abstract

A clock deskew circuit comprises a variable delay module and a control module. Included in the variable delay module are an input terminal for receiving a digital input clock signal, a control terminal for receiving an analog control signal, and a delay circuit which propagates the input clock signal from the input terminal to a buffer such that certain type signal edges (i.e., rising edges or falling edges) are delayed for a time interval which is varied in a continuous fashion by the magnitude of the control signal. Included in the control module is a feedback lead which receives the delayed clock signal from the buffer of the delay module, another lead which carries the input clock signal, and a control signal generating circuit. This control signal generating circuit sends the control signal to the control terminal of the delay module with a magnitude that increases the delay time interval when the delayed clock edges from the buffer lag the corresponding input clock edges by less than one clock cycle, and vice versa.

Loading the Abstract Image...

First Claim