Method and structure for providing fast conditional sum in a field programmable gate array
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 27, 1999
Issued Date -
N/A
app pub date -
May 9, 1997
filing date -
Sep 2, 1993
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A carry logic circuit for a field programmable gate array (FPGA) which allows a carry input signal to be propagated through the carry logic circuit without passing through a multiplexer of another series connected circuit element. The carry logic circuit uses a function generator of the FPGA to provide a propagate signal in response to first and second input signals provided to the carry logic circuit. Also described are methods for performing a carry logic function in an FPGA.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully