Integrated circuit floor plan optimization system
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United States of America Patent
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Apr 27, 1999
Grant Date -
N/A
app pub date -
Feb 11, 1997
filing date -
Feb 11, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
A method for planning floor allocation of an integrated circuit to each function is disclosed. To provide enough core space to each of the functions and to meet some cost functions such as space utilization requirement of each of the functions, the disclosed method divides the core space to a grid of elementary regions. Then, pieces of the core space are defined and the pieces containing the borders and the overlapping areas of the functions are identified. Then, the identified pieces are used shift the allocated capacities of the functions as to shift excess capacity or core space from the functions with excess capacity to the functions with a shortage of capacity.
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