Memory access mechanism for a parallel processing computer system with distributed shared memory

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United States of America Patent

PATENT NO 5898883
SERIAL NO

08368618

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Abstract

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To increase the capacity of usable memory of a parallel processing computer system as a whole and effectively utilize the address space without waste, a variable-length Global/Local allocation field is provided in a fixed-length address. When the field is locally set, the address is used as an address of a local memory area to which the local processor refers. When the allocation is globally set, the remaining address is a variable length logical processor number (this number is converted into a physical processor number) and a variable length offset address, for specifying a global memory area belonging to a processor out of the global areas of memories of a group of some of the processors, which global memory can be referred to by all the processors of the groups. A memory access interface executes memory access to the local or global area of the memory of the local processor or to the global area of the memory of another processor.

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Patent Owner(s)

Patent OwnerAddress
HITACHI LTD6-6 MARUNOUCHI 1-CHOME CHIYODA-KU TOKYO 1008280 ?1008280

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fujii, Hiroaki Hadano, JP 150 3047
Sukegawa, Naonobu Kokubunji, JP 27 1046
Tarui, Toshiaki Kokubunji, JP 43 1917

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