Processor-implemented method of controlling data access to shared resource via exclusive access control write-cache
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United States of America Patent
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May 4, 1999
Grant Date -
N/A
app pub date -
Jun 24, 1997
filing date -
Jun 24, 1997
priority date (Note) -
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Abstract
An atomic instruction is executed without the use of a dedicated atomic unit. A store instruction is transmitted from a front-end of one of a plurality of processors to a write-cache to cause the write-cache to obtain exclusive access to a control memory of a shared resource. A first signal is then transmitted to the front end of the processor indicating that the write-cache has obtained exclusive access to the control memory of the shared source. At least one next instruction is executed, and a second signal is transmitted from the front end to the write cache indicating that execution of the at least one next instruction has been completed. Data from the write cache is stored in the control memory of the shared resource in response to the second signal transmitted to the write cache.
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