Ultra low jitter differential to fullswing BiCMOS comparator with equal rise/fall time and complementary outputs
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United States of America Patent
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May 4, 1999
Grant Date -
N/A
app pub date -
Jun 13, 1996
filing date -
Jun 13, 1996
priority date (Note) -
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status (Latency Note)
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Abstract
A pair of complementary signals are switched between a high state and a low state such that the complementary signals are switched within a time period less than two gate delays. An inverter biases other inverters so that these two inverters are maintained at their threshold levels. The maintenance at the threshold values enable these two inverters to be switched quickly.
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