Semiconductor structure design and process visualization through the use of simple process models and intuitive interfaces
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United States of America Patent
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May 4, 1999
Grant Date -
N/A
app pub date -
Sep 24, 1996
filing date -
Sep 25, 1995
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Abstract
A semiconductor structure design and process visualization tool (10). A main menu (30) allows a user to add, edit or delete process steps (16a-f) to create a process flow in process flow window (12). Main menu (30) provides a set of process models to be selected from. The set of process models are simple first-order geometric models that require only physical parameters of a resulting device layer. Specific process conditions are not required. Semiconductor process and wafer representation tool applies the physical parameters to the corresponding process model to quickly create a cross-section (20) in cross-section window (22) corresponding to a selected process step (16d) in process flow window (12).
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