First-in, first-out integrated circuit memory device utilizing a dynamic random access memory array for data storage implemented in conjunction with an associated static random access memory cache
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United States of America Patent
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May 4, 1999
Grant Date -
N/A
app pub date -
Apr 1, 1997
filing date -
Apr 1, 1997
priority date (Note) -
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Abstract
An integrated circuit first-in, first-out ('FIFO') memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory ('DRAM') array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory ('SRAM') cache interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array.
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