Processor having a selectively configurable branch prediction unit that can access a branch prediction utilizing bits derived from a plurality of sources
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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May 4, 1999
Grant Date -
N/A
app pub date -
Jul 22, 1996
filing date -
Jul 22, 1996
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A processor and method for speculatively executing a branch instruction are disclosed. The processor includes a branch prediction unit for predicting a resolution of a speculative branch instruction, which is selectively configurable such that resolution of the speculative branch instruction is predicted in response to only an address of the speculative branch instruction or in response to branch history of at least one previously executed branch instruction. The processor also includes an address calculation unit for determining a target address in response to the predicted resolution of the speculative branch instruction. In one embodiment, the processor further includes configuration logic for dynamically configuring the branch prediction logic.
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