
US Patent No: 5,903,050
Number of patents in Portfolio can not be more than 2000
Semiconductor package having capacitive extension spokes and method for making the same
Stats
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May 11, 1999
Issued date -
Apr 30, 1998
filing date -
09/070,671
serial no -
In Force
status

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Abstract
Disclosed is a pair of conductive rings and method for making the conductive rings for introducing an integral network of capacitive structures around a semiconductor die of a semiconductor package. The pair of conductive rings include a ground rail ring that is defined around a semiconductor die pad that is configured to receive a semiconductor die. The ground rail ring has a first plurality of extension spokes that extend away from the ground rail ring. The pair of conductive rings further includes a power rail ring that is defined around the semiconductor die pad. The power rail ring has a second plurality of extension spokes that extend away from the power rail ring and toward the ground rail ring.
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First Claim
Related Publications
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
| Patent Owner | Address | Total Patents |
|---|---|---|
| LSI LOGIC CORPORATION | MILPITAS, CA | 4131 |
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Cheng, Wheling | Palo Alto, CA | 6 | 137 |
| Kirkman, Scott L | Redwood, CA | 3 | 183 |
| Thurairajaratnam, Aritharan | San Jose, CA | 31 | 208 |
Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 5,672,909 Interdigitated wirebond programmable fixed voltage planes | 18 | 1996 | |
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| 5,519,576 Thermally enhanced leadframe | 12 | 1995 | |
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| 5,691,568 Wire bondable package design with maxium electrical performance and minimum number of layers | 41 | 1996 | |
Patent Citation Ranking
Forward Cites
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 7,102,208 Leadframe and semiconductor package with improved solder joint strength | 2 | 2000 | |
| 6,627,977 Semiconductor package including isolated ring structure | 31 | 2002 | |
| 6,818,973 Exposed lead QFP package fabricated through the use of a partial saw process | 74 | 2002 | |
| 6,919,620 Compact flash memory card with clamshell leadframe | 1 | 2002 | |
| 6,798,047 Pre-molded leadframe | 5 | 2002 | |
| 6,777,789 Mounting for a package containing a chip | 6 | 2003 | |
| 6,965,159 Reinforced lead-frame assembly for interconnecting circuits within a circuit module | 4 | 2003 | |
| 6,750,545 Semiconductor package capable of die stacking | 13 | 2003 | |
| 6,927,483 Semiconductor package exhibiting efficient lead placement | 23 | 2003 | |
| 6,794,740 Leadframe package for semiconductor devices | 4 | 2003 | |
| 7,095,103 Leadframe based memory card | 0 | 2003 | |
| 6,879,034 Semiconductor package including low temperature co-fired ceramic substrate | 4 | 2003 | |
| 7,045,396 Stackable semiconductor package and method for manufacturing same | 77 | 2003 | |
| 7,008,825 Leadframe strip having enhanced testability | 24 | 2003 | |
| 6,876,068 Semiconductor package with increased number of input and output pins | 44 | 2003 | |
| 7,183,630 Lead frame with plated end leads | 7 | 2003 | |
| 6,897,550 Fully-molded leadframe stand-off feature | 3 | 2003 | |
| 7,485,952 Drop resistant bumpers for fully molded memory cards | 0 | 2003 | |
| 6,873,041 Power semiconductor package with strap | 16 | 2003 | |
| 7,071,541 Plastic integrated circuit package and method and leadframe for making the package | 1 | 2003 | |
| 7,245,007 Exposed lead interposer leadframe package | 44 | 2003 | |
| 7,057,280 Leadframe having lead locks to secure leads to encapsulant | 4 | 2003 | |
| 6,921,967 Reinforced die pad support structure | 4 | 2003 | |
| 6,998,702 Front edge chamfer feature for fully-molded memory cards | 7 | 2003 | |
| 6,846,704 Semiconductor package and method for manufacturing the same | 10 | 2003 | |
| 6,967,395 Mounting for a package containing a chip | 12 | 2003 | |
| 6,893,900 Method of making an integrated circuit package | 1 | 2003 | |
| 7,138,707 Semiconductor package including leads and conductive posts for providing increased functionality | 5 | 2003 | |
| 7,211,879 Semiconductor package with chamfered corners and method of manufacturing the same | 4 | 2003 | |
| 6,965,157 Semiconductor package with exposed die pad and body-locking leadframe | 9 | 2003 | |
| 7,115,445 Semiconductor package having reduced thickness | 1 | 2004 | |
| 7,057,268 Cavity case with clip/plug for use on multi-media card | 3 | 2004 | |
| 7,091,594 Leadframe type semiconductor package having reduced inductance and its manufacturing method | 7 | 2004 | |
| 7,170,150 Lead frame for semiconductor package | 2 | 2004 | |
| 6,844,615 Leadframe package for semiconductor devices | 7 | 2004 | |
| 7,005,326 Method of making an integrated circuit package | 5 | 2004 | |
| 7,190,062 Embedded leadframe semiconductor package | 24 | 2004 | |
| 7,067,908 Semiconductor package having improved adhesiveness and ground bonding | 4 | 2004 | |
| 7,211,471 Exposed lead QFP package fabricated through the use of a partial saw process | 43 | 2004 | |
| 7,202,554 Semiconductor package and its manufacturing method | 14 | 2004 | |
| 7,045,882 Semiconductor package including flip chip | 7 | 2004 | |
| 6,953,988 Semiconductor package | 18 | 2004 | |
| 7,217,991 Fan-in leadframe semiconductor package | 8 | 2004 | |
| 7,253,503 Integrated circuit device packages and substrates for making the packages | 41 | 2004 | |
| 7,001,799 Method of making a leadframe for semiconductor devices | 2 | 2004 | |
| 7,064,009 Thermally enhanced chip scale lead on chip semiconductor package and method of making same | 7 | 2004 | |
| 7,030,474 Plastic integrated circuit package and method and leadframe for making the package | 2 | 2004 | |
| 7,176,062 Lead-frame method and assembly for interconnecting circuits within a circuit module | 0 | 2005 | |
| 7,214,326 Increased capacity leadframe and semiconductor package using the same | 4 | 2005 | |
| 7,247,523 Two-sided wafer escape package | 15 | 2005 | |
| 6,995,459 Semiconductor package with increased number of input and output pins | 49 | 2005 | |
| 7,192,807 Wafer level package and fabrication method | 17 | 2005 | |
| 7,045,883 Thermally enhanced chip scale lead on chip semiconductor package and method of making same | 5 | 2005 | |
| 7,507,603 Etch singulated semiconductor package | 8 | 2005 | |
| 7,361,533 Stacked embedded leadframe | 20 | 2005 | |
| 7,572,681 Embedded electronic component package | 19 | 2005 | |
| 7,112,474 Method of making an integrated circuit package | 1 | 2005 | |
| 7,564,122 Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant | 1 | 2006 | |
| 8,410,585 Leadframe and semiconductor package made using the leadframe | 0 | 2006 | |
| 7,535,085 Semiconductor package having improved adhesiveness and ground bonding | 2 | 2006 | |
| 7,902,660 Substrate for semiconductor device and manufacturing method thereof | 15 | 2006 | |
| 7,968,998 Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package | 2 | 2006 | |
| 7,321,162 Semiconductor package having reduced thickness | 0 | 2006 | |
| 7,332,375 Method of making an integrated circuit package | 0 | 2006 | |
| 7,521,294 Lead frame for semiconductor package | 5 | 2006 | |
| 7,714,431 Electronic component package comprising fan-out and fan-in traces | 20 | 2006 | |
| 7,420,272 Two-sided wafer escape package | 16 | 2007 | |
| 7,723,210 Direct-write wafer level chip scale package | 6 | 2007 | |
| 7,692,286 Two-sided fan-out wafer escape package | 20 | 2008 | |
| 7,875,963 Semiconductor device including leadframe having power bars and increased I/O | 3 | 2008 | |
| 7,977,163 Embedded electronic component package fabrication method | 2 | 2009 | |
| 8,188,584 Direct-write wafer level chip scale package | 0 | 2010 | |
| 7,932,595 Electronic component package comprising fan-out traces | 4 | 2010 | |
| 8,324,511 Through via nub reveal method and structure | 0 | 2010 | |
| 8,294,276 Semiconductor device and fabricating method thereof | 0 | 2010 | |
| 8,440,554 Through via connected backside embedded circuit features structure and method | 0 | 2010 | |
| 8,390,130 Through via recessed reveal structure and method | 0 | 2011 | |
| 8,119,455 Wafer level package fabrication method | 1 | 2011 | |
| 8,298,866 Wafer level package and fabrication method | 0 | 2012 | |
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| 6,144,089 Inner-digitized bond fingers on bus bars of semiconductor device package | 6 | 1997 | |
| 6,249,047 Ball array layout | 58 | 1999 | |
| 6,376,282 Inner-digitized bond fingers on bus bars of semiconductor device package | 3 | 2000 | |
| 6,423,624 Ball array layout | 1 | 2000 | |
| 6,548,757 Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies | 36 | 2000 | |
| 6,448,640 Ball array layout in chip assembly | 15 | 2001 | |
| 6,630,732 Lead frames including inner-digitized bond fingers on bus bars and semiconductor device package including same | 1 | 2002 | |
| 6,784,367 Microelectronic device assemblies having a shielded input and methods for manufacturing and operating such microelectronic device assemblies | 0 | 2003 | |
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| 6,542,720 Microelectronic devices, methods of operating microelectronic devices, and methods of providing microelectronic devices | 24 | 1999 | |
| 6,718,163 Methods of operating microelectronic devices, and methods of providing microelectronic devices | 13 | 2003 | |
| 7,107,019 Methods of operating microelectronic devices, and methods of providing microelectronic devices | 6 | 2004 | |
| 7,593,708 Methods of operating electronic devices, and methods of providing electronic devices | 4 | 2006 | |
| 7,778,621 Methods of operating electronic devices, and methods of providing electronic devices | 2 | 2007 | |
| 8,036,629 Methods of operating electronic devices, and methods of providing electronic devices | 0 | 2010 | |
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| 6,222,246 Flip-chip having an on-chip decoupling capacitor | 43 | 1999 | |
| 6,707,145 Efficient multiple power and ground distribution of SMT IC packages | 5 | 2000 | |
| 6,920,051 Hybrid capacitor, circuit, and system | 22 | 2002 | |
| 6,822,526 Voltage plane with high impedance link | 2 | 2002 | |
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| 6,429,536 Semiconductor device | 21 | 2000 | |
| 6,448,639 Substrate having specific pad distribution | 25 | 2000 | |
| 6,833,611 Semiconductor device | 1 | 2003 | |
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| 6,326,677 Ball grid array resistor network | 17 | 1998 | |
| 7,180,186 Ball grid array package | 0 | 2003 | |
| 6,946,733 Ball grid array package having testing capability after mounting | 3 | 2003 | |
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| 6,437,385 Integrated circuit capacitor | 12 | 2000 | |
| 7,489,519 Power and ground ring snake pattern to prevent delamination between the gold plated ring and mold resin for wirebond PBGA | 0 | 2008 | |
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| 7,315,080 Ball grid array package that includes a collapsible spacer for separating die adapter from a heat spreader | 17 | 2004 | |
| 7,371,610 Process for fabricating an integrated circuit package with reduced mold warping | 16 | 2004 | |
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| 6,175,161 System and method for packaging integrated circuits | 41 | 1998 | |
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| 6,005,777 Ball grid array capacitor | 21 | 1998 | |
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| 6,424,032 Semiconductor device having a power supply ring and a ground ring | 7 | 2000 | |
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| 6,551,114 Semiconductor device having signal contacts and high current power contacts | 1 | 2001 | |
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| 6,774,479 Electronic device having a semiconductor chip on a semiconductor chip connection plate and a method for producing the electronic device | 2 | 2002 | |
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| 6,414,386 Method to reduce number of wire-bond loop heights versus the total quantity of power and signal rings | 7 | 2000 | |
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| 6,545,348 Package for a semiconductor device comprising a plurality of interconnection patterns around a semiconductor chip | 8 | 2000 | |
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| 6,222,260 Integrated circuit device with integral decoupling capacitor | 28 | 1998 | |
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| 6,028,349 Re-routing lead frame package and semiconductor memory package using the same | 1 | 1999 | |
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| 7,763,966 Resin molded semiconductor device and differential amplifier circuit | 0 | 2008 | |
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| 7,095,100 Semiconductor device and method of making the same | 9 | 2001 | |
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| 7,826,504 Active terahertz metamaterial devices | 2 | 2009 | |
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| 7,102,211 Semiconductor device and hybrid integrated circuit device | 1 | 2004 | |
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| 6,703,695 Semiconductor device and method for producing the same | 2 | 2003 | |
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| 6,246,072 Integrated circuit test pad | 0 | 1998 | |
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |