Importance

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Abstract

A two-stage switching regulator having low power modes responsive to load power consumption. A first stage of the regulator is a power factor correction (PFC) stage. A second stage is a pulse-width modulating (PWM) stage. When a load draws a high level of current, switching in both stages is enabled. Under certain conditions, switching in either one or both of the stages is disabled by the duty cycle for the corresponding switch falling to zero. When switching in both stages is enabled, as in a normal mode, switching in the PWM stage is then disabled in response to an error signal falling below a first error threshold. When switching in the PFC stage is enabled and switching in the PWM stage is disabled, as in a first low power mode, switching in the PFC stage is then disabled in response to a feedback voltage rising above a first feedback threshold. When switching in both stages is disabled, as in a second low power mode, switching in the PWM stage is then enabled in response to the error voltage rising above a second error threshold, higher than the first error threshold. When switching in the PFC stage is disabled and switching in the PWM stage is enabled, as in a third low power mode, switching in the PFC stage is enabled in response to the feedback voltage falling below the second feedback threshold. As a result of these low power modes, the switching regulator is highly efficient.

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First Claim