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Abstract

A high resolution clock circuit apparatus and a method of generating a high resolution clock output from a lower resolution clock input utilizes conventional technology. A standard clock generates a clock frequency which is divided by a flip-flop circuit and is applied to a low skew differential clock driver which distributes the clock into a plurality of separate outputs, each output is applied to a different length delay line. The output of each delay line is applied to a latching circuit, such as a low power octal ECL/TTL bidirectional translator. Each of the plurality of delay lines is sampled and a time word is latched when a time measurement is to be made. In this event, a control signal toggles from low to high which latches a digital word representing that subnanosecond interval of time. A shift register also receives the input clock frequency and includes a feedback loop and is applied to the latch circuit. The output of the two latches are input into a PROM used to convert the input code into a binary coded decimal.

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First Claim