Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach
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United States of America Patent
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May 11, 1999
Issued Date -
N/A
app pub date -
Jun 6, 1995
filing date -
Nov 8, 1994
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Abstract
A method of extracting layout parasitics for nets of an integrated circuit. The method creates a connectivity-based database (1104), where geometries of a layout are organized by nets of the circuit schematic. The method permits net-by-net extraction (1124) of layout parasitics using a connectivity-based database. A user can select a net or nets for extraction. A net is decomposed into polygon subsections, and parasitics are determined for these subsections. Layout parasitics for some of the decomposed geometries may be found in a predefined geometry library. A database is created containing nets and their extracted layout parasitics (1132). A netlist format file may be generated from this database of extracted parasitics to provide for back annotation of layout parasitics into a circuit schematic for further circuit analysis.
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