Scalable multi-processor architecture for SIMD and MIMD operations
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United States of America Patent
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May 11, 1999
Issued Date -
N/A
app pub date -
Mar 21, 1996
filing date -
Jan 16, 1996
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A multiprocessor device capable of operating in both MIMD and SIMD modes which includes an array of parallel processor elements connected via link ports on each element. A multiplexing means is provided for dynamically configuring the connection topology between link ports so that a direct connection can be made between any two processor elements. Local dual-ported memory is associated with each processor element in the array and is connected through a first port to its associated processor element and through a second port to a multidimensional DMA controller. The DMA controller transfers data autonomously between the processor elements and global resources, including a global memory. For SIMD mode operations, the DMA controller broadcasts duplicate instructions to the dual-ported memory associated with each processor element, and the instructions are then executed by each processor in synchrony.
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