Method for the preparation of lead-on-chip assemblies
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United States of America Patent
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May 18, 1999
Issued Date -
N/A
app pub date -
Oct 3, 1996
filing date -
Oct 3, 1996
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In accordance with the present invention, alternate lead-on-chip assembly methodologies have been developed which eliminate the use of a three layer film bonded to the leadframe, as currently employed in the art. According to the present invention, a dielectric paste is dispensed directly onto the top surface of the silicon die instead of the thermoplastic tape currently employed in the art. This approach required the development of apparatus and methods which meet the following requirements, e.g., 1) the method (and apparatus employed therefor) must provide comparable units/hour throughput to existing LOC assembly methods, and 2) the method must provide equivalent or superior package reliability when compared with tape bonded LOC packages. The invention method (and apparatus suitable for use therefor) satisfies these needs.
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