Importance

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Abstract

A power down circuit for a memory device is provided that includes a burn-in voltage detector to generate a burn-in voltage detecting signal to control a power down signal when a burn-in voltage reaches a predetermined level. The power down circuit enhances a burn-in function by operating the memory cells and peripheral circuits for a relatively long time at a high level voltage when a burn-in is performed on the memory device with an auto power down function. Thus, the memory device reliability is also enhanced. The memory device includes a power down timer for generating a power down signal to control an input/output operation of a memory cell in response to a plurality of address transition detecting signals, a plurality of data input detecting signals, a chip select detecting signal, a write mode detecting signal and the burn-in voltage detecting signal.

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First Claim