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Abstract

In an IBM PC/AT-compatible computer system, the frequency of the CPU bus clock signal is detected via a hardware apparatus in the I/O interface chipset. The CPU reads the hardware-detected clock frequency from an I/O register. In one embodiment, one bit of the data returned from the register indicates whether the clock frequency indicated by the remainder of the bits is valid. The CPU can trigger the hardware to autodetect the clock frequency by writing arbitrary data to the same address. The hardware clock frequency detection circuitry operates by, in response to a start signal, counting the number of cycles of the CPU clock signal which occur within a predefined number of cycles of the ISA-bus OSC signal. The start signal can be asserted in response negation of the system reset signal, or in response to a write access on the ISA bus to a predefined I/O register, or both. The clock frequency detection apparatus can include validation circuitry which asserts the validity signal only after the count is complete, and only if the count value has not exceeded a predetermined maximum count.

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First Claim