Importance

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Abstract

The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away. According to a second aspect of the invention, high fanout signals can be distributed to any tile in the array. A signal on a horizontal long line traverses a row of tiles, in which it makes contact with the logic block in each tile through hex lines and single-length lines. The horizontal single-length lines connected to some horizontal hex lines can programmably drive vertical long lines. Using these programmable connections, the signal on the horizontal long line bus is transferred to the vertical long lines. From the vertical long lines, a high-fanout signal is delivered to an array of tiles.

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First Claim