Mask write enablement for memory devices which permits selective masked enablement of plural segments
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United States of America Patent
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May 25, 1999
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Oct 20, 1993
filing date -
Aug 14, 1989
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Abstract
A Mask Write mode for a semiconductor memory responds to an enable command. This permits a by-four chip to provide parity information for four sectors of memory. The invention allows the latching of mask data on a rising edge of CAS so that new mask data can be entered in Page Mode.
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