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Abstract

A phase-locked loop (PLL) system including a voltage-controlled oscillator, a divider, a phase detector, and a low-pass filter. The voltage-controlled oscillator has two control input terminals S and L and generates a pulse signal having an oscillation frequency fout2. The divider generates a pulse signal having a frequency fout2/N2 from the output signal of the oscillator. The phase detector detects the phase difference between the pulse signal output from the divider and the a pulse signal having a reference frequency fref and generates an error signal corresponding to the phase difference detected. The low-pass filter integrates the error signal. The output signal of the low-pass filter is input to the control input terminal S of the oscillator. A control signal is input to the control input terminal L of the oscillator to control the free-running frequency of the oscillator.

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