Importance

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Abstract

An interface circuit included in a ring interconnected group of processing elements includes a backup FIFO to temporarily store information received by the interface circuit when it receives an indication that it temporarily should not forward information to the next processing element in the ring. The interface circuit can receive such an indication, for example, when it receives a signal from the downstream processing element in the ring indicating that the downstream circuit is unable to receive information, or when it receives an information packet requesting a read from the core of the processing element. When the interface circuit receives such an indication, it de-asserts an outgoing ready signal to the upstream processing element in the ring, which should cause the upstream processing element to stop sending information. Once the interface circuit receives an indication that it again may transmit information, the contents of the backup FIFO is released to the output of the interface and possibly is mixed with read data from the core. The control of the flow of information into and out of the backup FIFO is accomplished by storing information in single-bit registers within the control logic of the ASIC in which the interface circuit is implemented that identifies the contents of the various registers in the backup FIFO. In this manner, the information flow into and out of the backup FIFO may be controlled by inspecting the single-bit registers rather than decoding the contents of the backup FIFO itself.

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First Claim