Method and system for layout and schematic generation for heterogeneous arrays
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United States of America Patent
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Jun 8, 1999
Issued Date -
N/A
app pub date -
Nov 12, 1997
filing date -
Dec 12, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and system for defining, placing and routing kernels for a family of integrated circuits is provided. The integrated circuits are defined using repeatable row and column circuit types. Kernels are defined by the intersections of the row and column circuit types in the array. The kernels are placed and routed automatically for each member of the family of integrated circuit arrays, each member being generally characterized by a different size, i.e., a different number of repeatable row or column circuit types.
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