Importance

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Abstract

Several graphics processing elements are interconnected in a ring using a plurality of individual busses. Each bus interconnects a pair of the graphics processing elements and includes a like group of signal lines for transferring graphics command signals and information signals between graphics processing elements in the ring. Each group of signal lines includes: a group of information signal lines for transferring information between the processing elements; a clock signal line for transferring a clock signal associated with the information signals on the information signal lines to the next processing element in the ring; a ready signal line, on which a ready signal is transferred from a first graphics processing element to a previous graphics processing element in the ring, the ready signal indicating the ability of the first graphics processing element to receive information from the previous graphics processing element; and a group of type signal lines, for transferring type signals indicating the type of operation to be performed on information on the information signal lines. One of the graphics processing elements is a host interface processing element and is coupled to a host processor to receive commands and information signals to be forwarded to the other graphics processing elements in the ring. Each of the graphics processing elements includes: a core processing unit; an interface unit, including a pass through path, which permits command and information signals to be transferred directly through the interface unit to another graphics processing element in the ring, and a backup path, for temporarily storing the forwarded command and information signals; and a plurality of buffers, coupled between the interface unit and the corresponding core processor, for temporarily storing the command and information signals for transfer to the core processing unit.

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First Claim