Parallel processing building block chip
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United States of America Patent
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Jun 8, 1999
Grant Date -
N/A
app pub date -
Feb 25, 1997
filing date -
Feb 25, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A parallel processing building block (PPBB) chip comprises a low performance programmable digital signal processor (DSP) to implement relatively low intensity processing functions and includes a bus control for address and data communication. A medium performance programmable DSP to implement relatively medium intensity processing functions and includes a bus control for address and data communication. A high performance programmable DSP to implement relatively high intensity processing functions and includes a bus control for address and data communication. A serial and parallel bus controller provides external connectivity to a host system bus. A data router controller is connected to the bus control of each of the high, medium and low DSP's, and to the bus controller, and includes a memory interface controller for connection to an external RAM system, and a data router for controlling data movement between any of the high, medium and low DSP's, the memory interface controller, the bus controller as well as to other PPBB chips.
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