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Abstract

A memory cell includes non-volatile and volatile storage elements and is configured to dynamically alter threshold voltages of the non-volatile storage elements to store states of the volatile storage elements. The volatile storage elements may be stacked gate PMOS transistors, one of which may include a gate structure having a poly-silicon control gate disposed over a poly-silicon floating gate. The control gate and floating gate may be separated by a coupling dielectric, which may be an ONO stack or a deposited oxide. The gate structure may be disposed over an active area of a substrate including a drain and a source of the PMOS transistor. The active area may be disposed in an n-well of the substrate. A first of the volatile storage elements may comprise an NMOS transistor which is formed in a p-well of the substrate. The p-well may further be disposed in an n-well. In a further embodiment, a memory cell includes non-volatile storage elements configured to power up so that a first of the non-volatile storage element undergoes band-to-band tunneling induced hot electron injection onto its floating gate while a second of the non-volatile storage elements undergoes Fowler-Nordheim tunneling of electrons off its floating gate. The memory cell may also include volatile storage elements and/or select transistors coupled to the non-volatile storage elements. In another embodiment a memory or other integrated circuit includes either of the above memory cells.

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First Claim