Semiconductor chip scale package and method of producing such
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United States of America Patent
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Jun 22, 1999
Grant Date -
N/A
app pub date -
Dec 23, 1996
filing date -
Dec 22, 1995
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A semiconductor chip scale package and method of producing the package are disclosed. The package has a semiconductor chip having signal leading bumps. A PCB is electrically connected to the chip, thus transmitting input and output signals. A plurality of solder balls are formed on the lower surface of the PCB and are used as signal input and output terminals. An epoxy resin layer bonds the chip to the PCB. The PCB consists of a polymer resin substrate, a copper circuit pattern and a solder mask. The copper circuit pattern has a chip bump land and a solder ball land. The lands electrically connect the signal leading bumps to the solder balls. The package has a package size being similar to or slightly larger than a semiconductor chip within 120 % of the size of the chip.
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