Methods of planarizing structures on wafers and substrates by polishing

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United States of America Patent

PATENT NO 5916453
SERIAL NO

08717266

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is then formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

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Patent Owner(s)

  • FUJITSU LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Beilin, Solomon I San Carlos, CA 53 3551
Chou, William T Cupertino, CA 29 1261
Lee, Michael G San Jose, CA 77 2745
Moresco, Larry Louis San Carlos, CA 7 306
Wang, Wen-chou Vincent Cupertino, CA 45 2529

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