Photolithographic alignment marks based on circuit pattern feature
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United States of America Patent
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Jun 29, 1999
Issued Date -
N/A
app pub date -
May 2, 1997
filing date -
Jun 1, 1995
priority date (Note) -
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status (Latency Note)
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Abstract
Photolithographic alignment marks (e.g., mask and measurement overlay marks) are formed of a pattern of very small marks using the design configuration and rule of a circuit pattern feature. A relatively large mark comprising a pattern of small marks modeled after the circuit pattern feature results in an etch rate within the mark area that is substantially the same as the etch rate in the circuit pattern (e.g., cell or peripheral circuit) area. This allows for simultaneous formation of circuit pattern features, and the alignment marks, in a common etching step, while avoiding underetching (shallow etch depth) due to a microloading effect. In this manner, proper formation of readily detectible marks is ensured.
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