Synchronous read channel employing a frequency synthesizer for locking a timing recovery phase-lock loop to a reference frequency

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United States of America Patent

PATENT NO 5917668
SERIAL NO

08822174

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Abstract

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A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To ensure a small frequency error when timing recovery acquisition mode is entered, the timing recovery phase-lock loop (PLL) is first locked to a nominal read frequency which is the same as the write frequency. This is accomplished by multiplexing the output of the write frequency synthesizer into the timing recovery PLL in a lock-to-reference mode. Thereafter, the analog signal from the read head is multiplexed into the timing recovery PLL in order to acquire the actual frequency and phase of an acquisition preamble recorded prior to the user data.

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Patent Owner(s)

Patent OwnerAddress
CIRRUS LOGIC INC800 WEST 6TH STREET AUSTIN TX 78701

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Behrens, Richard T Louisville, CO 74 2643
Dudley, Trent Littleton, CO 22 623
Glover, Neal Broomfield, CO 48 2002
Welland, David R Austin, TX 151 3701

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