Importance

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Abstract

The present invention provides for a method of operation for a memory system having a memory controller integrated circuit, a plurality of memory integrated circuits, particularly DRAMs, and a plurality of signal lines connected to memory controller and the memory integrated circuits. To avoid the problem of the problem of skew between the signals to and from the DRAMs, the method of operation determines a delay between an issued read command and receipt of signals from a selected DRAM by the controller integrated circuit in response to the read command, and sets a read delay in the selected DRAM. Further steps in the operation include the determination of the delay between an issued read command and the receipt of signals from each one of the DRAMs by the memory controller integrated circuit in response to a read command, and setting the read delay in each one of the DRAMs so that the delays between an issued read command and receipt of signals from each one of the DRAMs by the controller integrated circuit are equal. Besides the operating speeds of the individual DRAMs, skew which is dependent upon the position of the DRAMs along a bus caused by bus loading effects, signal reflections, noise, etc., is reduced, if not eliminated.

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First Claim