Importance

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Abstract

The present invention provides a data processing circuit with a power saving mode of operation. The data processing circuit comprises a clock generator for generating a clock signal, and a plurality of clocked circuit elements. In accordance with the present invention, a main bus is arranged to provide the clock signal to the plurality of clocked circuit elements in a first mode of operation, and a power saving bus separate from the main bus is arranged to provide the clock signal to a subset of said plurality of clocked circuit elements in a power saving mode of operation. Further, a clock switcher circuit is provided for switching the clock signal to either the main bus or the power saving bus dependent on the mode of operation. By this approach, the clock signal is routed only to the subset of circuit elements which require to be clocked in each mode of operation, and the length of bus routing and number of loads attached to the clock bus can be reduced for each operating mode, thus reducing the power consumption across all operating modes of the device.

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First Claim