Operand cache addressed by the instruction address for reducing latency of read instruction
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United States of America Patent
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Jul 6, 1999
Grant Date -
N/A
app pub date -
Mar 26, 1996
filing date -
Mar 26, 1996
priority date (Note) -
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status (Latency Note)
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Abstract
A structure for, and a method of operating, an operand cache to store operands retrieved from a memory. An instruction requiring an operand stored in the memory, is allowed to speculatively execute in an execution unit of a processor using an operand stored in an entry (corresponding to the address of the instruction) of the operand cache. When the actual operand is later retrieved from the memory it is compared to the cached operand used for speculative execution. If the cached and actual operands are unequal then the speculatively executed instruction and all subsequent instructions are aborted and the processor resumes execution at the address of the instruction that was speculatively executed.
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